1. Field of the Invention
The present invention relates to an overcurrent protection device that is used with a power supply (e.g. a DC-DC converter) supplying an intended direct-current voltage to a load circuit by controlling the duty-ratio of a main switch (e.g. a Field Effect Transistor, or an FET) and controls the output current by reducing the on-time of the main switch when an overcurrent flows through the main switch in the on state.
2. Related Art
A switching regulator supplies an intended direct-current voltage to a load circuit by controlling the duty-ratio of the main switch. One such switching regulator is a Pulse Width Modulation (PWM) switching regulator, and there are two types for the PWM switching regulators: a buck type converter and a boost type converter. The following will give an account of a switching regulator using a PWM buck type converter.
When the on-time and off-time of the main switch for each cycle are Ton and Toff, respectively, and the input voltage of the switching regulator is Vin, the output voltage Vout is found by the following equation:Vout=Ton/(Ton+Toff)·Vin  (1).
In order to keep the output voltage Vout constant, in the PWM, the ratio of the on- and off-times of the main switch is adjusted so that the error voltage (Vout-Vref), which is a difference between the output voltage Vout and the reference voltage Vref, becomes small. In the event that an overcurrent is detected, the main switch is protected from breakdown by controlling the output current by reducing the on-time Ton and thereby lowering the output voltage Vout.
Additionally, a switching regulator has been suggested that stops the PWM operations when an overcurrent is detected, instead of reducing the on-time Ton (cf. Japanese Laid-Open Patent Application Publication No. 2002-27737). FIG. 1 is a circuit diagram illustrating a configuration of the switching regulator (a step-down DC-DC converter). As shown in FIG. 1, the switching regulator 19 comprises an overcurrent protection device 1900, a main switch 1901, a rectifier switch 1902, a controller 1903, an AND circuit 1904, an inductor 1905, a capacitor 1906, a control terminal 1907, an input terminal 1908, an output terminal 1909, and an edge pulse generator 1910. The main switch 1901 is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the rectifier switch 1902 is an N-channel MOSFET.
The overcurrent protection device 1900 includes an RS-flipflop 1900a, a comparator 1900b, and a constant voltage source 1900c. The constant voltage source 1900c is made up of a resistor 1900c1 and a constant current source 1900c2. The edge pulse generator 1910 includes a switch 1910a, a NOR circuit 1910b, NOT circuits 1910c and 1910f, a capacitor 1910d, and a resistor 1910e. 
The main current path of the switching regulator 19 is from the input terminal 1908 to the output terminal 1909 through the main switch 1901 and the inductor 1905. A load circuit (omitted from FIG. 1) is connected to the output terminal 1909. A voltage Vin is applied to the input terminal 1908.
The control signal that controls the switching regulator 19 under PWM control is input to the edge pulse generator 1910 from the control terminal 1907. By the control signal, the on/off of the main switch 1910 is controlled so as to alternate with the rectifier switch 1902 for each cycle. The main switch 1901 is an FET.
The switching regulator 19 is a synchronous converter, and after the main switch 1901 is turned off and then a dead-time period (i.e. a time period required to avoid having both the main switch 1901 and the rectifier switch 1902 conduct at the same time) elapses, the rectifier switch 1902 is turned on. Herewith, energy stored in the inductor 1905 is supplied to the load circuit as a current. The current path for the rectification of the switching regulator 19 is from the inductor 1905 to the ground through the output terminal 1909 and the load circuit.
The inductor 1905, together with the capacitor 1906, makes up an LC filter. Herewith, a ripple in the output voltage is reduced and then the output current is smoothed.
The edge pulse generator 1910 inputs a reset signal synchronizing with the control signal to a reset terminal of the RS-flipflop 1900a. A pulse width Treset19 of the reset signal is determined by a time constant of an RC integration circuit composed of the capacitor 1910d and the resistor 1910e. 
A set signal is input to a set terminal of the RS-flip-flop 1900a from the comparator 1900b. For each cycle, the RS-flip-flop 1900a is set by the set signal and reset by the reset signal. Due to the rising and trailing edges of the pulses of the set and reset signals, the reverse output /Q of the RS-flipflop 1900a repeats the state transition between a high level and a low level on a cyclic basis.
The following explains the case in which a positive logic is used for a logic circuit.
The AND circuit 1904 inputs to the controller 1903 a signal which is a product of the reverse output /Q and the control signal. According to the signal, the controller 1903 drives the main switch 1901 and the rectifier switch 1902 alternately turning them on/off so that there is no time period in which these two switches are on at the same time.
The overcurrent protection device 1900 monitors a current flowing through the main switch 1901 by comparing a voltage drop ΔV(t) between drain and source of the main switch 1901 and a reference voltage ΔVref.
FIG. 2 is a timing chart showing a normal operation of the switching regulator 19 over one PWM cycle. In FIG. 2, the horizontal axis indicates time, and the vertical axis indicates a voltage or a current. In the present specification, “H” and “L” denote a high and a low level, respectively.
Waveform 2001 shows voltage levels of the control signal, Waveform 2002 shows gate-voltage levels of the rectifier switch 1902, Waveform 2003 shows gate-voltage levels of the main switch 1901, Waveform 2004 shows the amount of the current flowing through the inductor 1905, Waveform 2005 shows levels of the output voltage provided from a circuit composed of the main switch 1901 and the rectifier switch 1902, Waveform 2006 shows voltage levels of the set signal, Waveform 2007 shows voltage levels of the reset signal, and Waveform 2008 shows voltage levels of the reverse output /Q.
As shown in FIG. 2, at a time t190 the control signal switches from L to H (Waveform 2001). In synchronization with this, the reset signal switches to H (Waveform 2007) and the reverse output /Q switches to H (Waveform 2008). Herewith, the switching operations of the main switch 1901 and the rectifier switch 1902 for one cycle are started.
After a delay time duration Td191 elapses, the rectifier switch 1902 is turned off (Waveform 2002). Then, after a delay time duration Td192 elapses, the main switch 1901 is turned on (Waveform 2003). Note that the delay time duration Td191 is determined by a circuit of the controller 1903. The delay time duration Td192 is also determined by the circuit of the controller 1903, and this is a dead-time period provided to avoid having both the main switch 1901 and the rectifier switch 1902 conduct at the same time.
Subsequently, during a risetime duration Td193, the output voltage V(t) provided from the circuit composed of the main switch 1901 and the rectifier switch 1902 rises from 0 to Vin (Waveform 2005). Herewith, the inductor current I(t) flows (Waveform 2004) and is supplied to the load circuit.
In this case, as shown in the following equation, the inductor current I(t) increases with a slope defined by a potential difference (Vin−Vout) between the input terminal 1908 and the output terminal 1909, and an inductance value L1905 of the inductor 1905.I(t)=(Vin−Vout)/L1905·(t−t191)  (2).Here, a time t191 is a time when the current I(t) starts increasing, and is defined by:t191=t190+Td191+Td192.
When the current I(t) flows through the main switch 1901, a voltage drop ΔV(t) occurs (Waveform 2005) between drain and source of the main switch 1901, due to an on-resistance Ron1901 of the main switch 1901 and the current I(t). This voltage drop ΔV(t) can be found by the following equation:ΔV(t)=Vin−V(t)  (3).
The comparator 1900b monitors whether an overcurrent is flowing through the main switch 1901 by comparing the voltage drop ΔV(t) and the reference voltage ΔVref.
As shown in FIG. 2, before a time (t191+Td193), the voltage drop ΔV(t) becomes larger than the reference voltage ΔVref (i.e. ΔV(t)>ΔVref). During the period between the time (t191+Td193) and a time (t193+Td195), the voltage drop ΔV(t) is equal to or smaller than the reference voltage ΔVref (ΔV(t)≦ΔVref) (Waveform 2005). Therefore, before the time (t191+Td193), the comparator 1900b judges that an overcurrent is flowing through the main switch 1901 and switches the set signal to H. After the time (t191+Td193), the comparator 1900b keeps the set signal at H until a delay time duration Td194 elapses. The delay time duration Td194 is a circuit delay time of the comparator 1900b. 
However, since an overcurrent is in fact not flowing, the edge pulse generator 1910 keeps the reset signal at H until a margin Tm19 elapses after a time t192 (Waveform 2007). From the time t1 go onward, a duration of time while the reset signal is set at H is referred to hereinafter as “Treset19”.
At a time t193, the control signal switches to L (Waveform 2001). Then, after a delay time duration Td195 elapses, the gate voltage of the main switch 1901 switches to H (Waveform 2003), and the main switch 1901 is turned off.
After a delay time duration Td197 elapses, the gate voltage 102 of the rectifier switch 1902 switches to H (Waveform 2002), and the rectifier switch 1902 is turned on. Hereby, energy stored in the inductor 1905 is supplied as a current to the load circuit through the rectifier switch 1902.
Note that the above delay time duration Td195 is a circuit delay time of the controller 1903. The delay time duration Td197 is also a circuit delay time of the controller 1903, and is a dead-time period of the main switch 1901 and the rectifier switch 1902.
As described above, once the main switch 1901 is turned off, the voltage drop ΔV(t) largely exceeds the reference voltage ΔVref (Waveform 2005). Accordingly, the comparator 1900b judges that an overcurrent is flowing though the main switch 1901, and then the set signal is switched from L to H with a delay for a circuit delay time (Waveform 2006). Here, the circuit delay time is shorter than the delay time duration Td197.
Herewith, the reverse output /Q switches to L (Waveform 2008), and the control signal is kept at L until the signal switches to H again.
FIG. 3 is a timing chart showing an operation of the switching regulator 19 performed at the time when an overcurrent occurs. In FIG. 3, the horizontal axis indicates time, and the vertical axis indicates a voltage or a current. Waveform 2101 shows voltage levels of the control signal, Waveform 2102 shows gate-voltage levels of the rectifier switch 1902, Waveform 2103 shows gate-voltage levels of the main switch 1901, Waveform 2104 shows the amount of the current flowing through the inductor 1905, Waveform 2105 shows levels of the output voltage provided from the circuit composed of the main switch 1901 and the rectifier switch 1902, Waveform 2106 shows voltage levels of the set signal, Waveform 2107 shows voltage levels of the reset signal, and Waveform 2108 shows voltage levels of the reverse output /Q.
Owing to short-circuiting of the load circuit and like, when an overcurrent flows through the main switch 1901 and thereby the voltage drop ΔV(t) exceeds the reference voltage ΔVref (Waveform 2105), the comparator 24 judges that an overcurrent is flowing through the main switch 1901 and switches the set signal to H (Waveform 2106). Here, a case in which the comparator 1900b keeps the set signal constantly at H will be explained (Waveform 2106).
As described above, during the time duration Treset19, the PWM operations are continued regardless of the set signal. After the time duration Treset19 elapses, the reset signal switches from H to L and thereby the RS-flipflop 1900a is reset. Here, since the set signal is at H, the reverse output /Q switches from H to L. Hereby, the main switch 1901 is turned off and then the overcurrent is cut off. As a result, the main switch 1901 is protected from breakdown caused by the overcurrent.
In order to prevent an erroneous detection of the overcurrent in the normal operation, the time duration Treset19 must be set longer than the period between the times t190 and t192 as described above. The period between the times t190 and t192 is equal to the total sum of the delay time durations Td191, Td192, Td193, and Td194. Therefore, the time duration Treset19 has to satisfy the following inequality:Treset19>Td191+Td192+Td193+Td194  (4).
In order to prevent the erroneous detection of the overcurrent in this manner, a period Ton(min)19 during which the main switch 1901 is kept on (hereinafter, “minimum on-time”) arises whether or not an overcurrent is flowing through the main switch 1901. This minimum on-time Ton(min)19 can be found by:Ton(min)19=Treset19−Td191−Td192+Td196  (5).where Td196 is a duration of time from when the reset signal switches from H to L until the main switch 1901 is turned off (see, FIG. 3).
The following inequality can be derived from the inequality (4) and the equation (5):Ton(min)19>Td193+Td194+Td196  (6).
Namely, the minimum on-time Ton(min)19 has a lower limit, and is always larger than the value of the right hand side of the inequality (6).
However, when the RC time constant circuit, which determines the time duration Treset19, in the edge pulse generator 1910 is integrated on a semiconductor substrate, the variations in the diffusion resistance and the temperature fluctuation of the integrated RC time constant are around +200% to −50%. This causes variations in the time duration Treset19. Additionally, by the same token, variations in each of the time durations Td191, Td192, Td193 and Td194 arise.
When variations in the time durations Treset19, Td191, Td192, Td193 and Td194 are δTreset19, δTd191, δTd192, δTd193 and δTd194, respectively, δTreset19 has inequality:δTreset19>δTd191+δTd192+δTd193+δTd194  (7),where δTreset19, δTd191, δTd192, δTd193, and δTd194 are all positive numbers.
In order to prevent an erroneous detection of the overcurrent regardless of these variations, it is required to include the margin Tm19 in the time duration Treset19.Treset19=Td191+Td192+Td193+Td194+Tm19  (8).
Furthermore, according to the equations (5) and (8), the minimum on-time Ton(min)19 has equation:Ton(min)19=Td193+Td194+Td196+Tm19  (9).
Since Tm19 must be larger than at least δTreset19, Tm19 has to satisfy the following inequality:Tm19>δTd191+δTd192+δTd193+δTd194  (10).
Here, coefficients of the variations (i.e. relative errors) in the time durations Td191, Td192, Td193, and Td194 are α191, α192, α193, and α194, respectively. These coefficients are defined by:αi=δTdi/Tdi(i=191, 192, 193, 194)  (11),and then the above inequality (10) can be expressed as follows:Tm19>α191·Td191+α192·Td192+α193·Td193+α194·Td194  (12).
Namely, in order to prevent an erroneous detection of the overcurrent, the minimum on-time Ton(min)19 becomes considerably larger than the minimum value of the right hand side of the inequality (6), (Td193+Td194+Td196). As a result, the time period during which the overcurrent flows through the main switch 1901 becomes long and a current peak of the current I(t) becomes large, which increases the likelihood that the main switch 1901 may be destroyed.
Additionally, since the on-resistance Ron1901 has a positive temperature characteristic, when a MOSFET is used for the main switch 1901, the voltage drop ΔV(t) becomes larger as temperature reaches higher. Consequently, if the reference voltage ΔVref is constant independent of temperature, it becomes difficult to detect an overcurrent when temperature is low. This will also increase the chance that the main switch 1901 will be destroyed by the overcurrent.
A switching regulator using a PWM buck type converter has been explained as an example. In general, similar problems exist also in switching regulators that supply a predetermined voltage by controlling the on/off of the main switch on a cyclic basis.